Responsibilities:
• Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
• Layout of sensitive analog components including resistors, capacitors, and inductors.
• Block level and top-level layout through full verification flow including RLC extraction, DRC, LVS, and DFM checking.
• Co-work with designers on block-level and top-level floor-planning.
• Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
• Top-level layout integration and verification, schedule management.
Requirements:
• 5+ years experience in custom RF/analog layout with extensive knowledge on deep sub-micron CMOS (28nm, FINFET’s, etc.).
• Knowledgeable on layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing.
• Must recognize failure prone circuit and layout structures, proactively work with circuit designer for best approach to problems.
• High-level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
• Familiarity of CADENCE layout tools and Mentor Graphics verification tools.
• Excellent communication skills and able to work with cross-functional teams.