· Bachelors with 15+ years of relevant industry experience, or Masters with 13+ years or PhD with 10+ years in Electrical Engineering or related field preferred.
· Experience in developing test benches using SystemVerilog UVM, testcase development skills for constrained random and directed scenarios
· Experience in MCU/CPU Verification at processor level and at sub-system level both.
a. Strong understanding of CPU architectures, instruction sets (x86, ARM, RISC-V flavors).
b. Core architecture/micro-architecture verification
c. Multi-processor Cache (L2/L3) Coherency, Memory Hierarchy Verification
· Good object-oriented programming skills in C++/SV, scripting languages like Python/Perl.
· Familiarity with Formal Verification.
· DMS Verification experience or knowledge preferred.
· Excellent simulation debugging and problem-solving skills
· Ability to adopt new methodologies and techniques, promote them across the organization
· Experience and knowledge of EDA tools: Simulator (Synopsys VCS or Cadence Xcelium or Siemens Questasim or equivalent tools), debugging tools (Synopsys Verdi or Cadence Simvision)