Contract Duration: 6 months contract
Responsibilities:
• Participates in the definition of architecture and microarchitecture features of the block being designed.
• Creates prototypes, simulates models, and specifies systems requirements.
• Architect and implement multi-FPGA partitioning solutions
• Design and debug high-speed interfaces including Ethernet, PCIe, and DDR
• Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.
• Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure–Simulation Validation– Lab Based Silicon Validation
• Drive trade-off analysis to benefit customer experience and optimization of target technology resources for cost/size/power/performance/feature
Requirements:
• BE (BS/MS/Ph. D. preferred) in Computer/Electrical Engineering or Computer Science with 10+ years of working experiences in architecture development
• Experience with FPGA HDL development, simulation and analysis, static timing analysis, utilizing the VHDL and/or Verilog language
• Experience with RoCEv2 (RDMA over Converged Ethernet) stack, including RDMA READ/WRITE operations, Queue Pair (QP) management, and congestion control
• Experience with NVMe over Fabrics RTL development, facilitating direct data transfer between host memory and storage targets
• Experience with high-speed interfaces tune, specially PCIe Gen4/5/6 and 100G/200G/400G Ethernet MAC/PCS
• Self-motivated problem-solver with an ability to work well in a team
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change. |